1. Field of the Invention
The present invention relates to a circuit and related method for correcting over-erased flash memory cells, and more particularly, to a circuit and method for continuously applying a correction voltage to a bitline coupled to an over-erased flash memory cell to correct the over-erased flash memory cell.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram of a prior art flash memory circuit 10. The flash memory circuit 10 is disclosed in U.S. Pat. No. 5,642,311 xe2x80x9cOvererase correction for flash memory which limits overerase and prevents erase verify errors.xe2x80x9d The flash memory circuit 10 comprises a flash memory array 20 and a processor 34 for controlling the operations of the flash memory circuit 10 to perform reading, erasing, or writing to the flash memory array 20. The flash memory array 20 comprises a plurality of flash memory cells 22. Each flash memory cell 22 comprises a source S, a control gate G, and a drain D, wherein the source S is electrically connected to a voltage source Vss, the control gate G is electrically connected to a corresponding wordline 23, the drain D is electrically connected to a bitline 24, and each bitline 24 is electrically connected to a bit line pull-up circuit 26. When the processor 34 performs reading, erasing, or writing to a flash memory cell 22, related control signals are respectively sent to a row decoder 30 and a column decoder 28 to control a voltage of the wordline 23 and the bitline 24 connected to the appropriate flash memory cell 22. The flash memory circuit 10 further comprises a reference memory array 38 for outputting a reference signal, a sense amplifier 36 for comparing the reference signals outputted from the reference memory array 38 with the signals outputted from the flash memory cells 22, a data register 40 for temporarily storing data outputted from the flash memory array 20, and a power source 32 for providing the electrical power needed by the flash memory circuit 10.
Currently, the most well-known and commonly used flash memory erasing method is called Fowler-Nordheim tunneling (FN tunneling). When the processor 34 performs an erasing procedure on a flash memory cell 22, a voltage pulse is continually applied to the flash memory cell 22. The erasing voltage pulse generates an electromotive force (EMF) with a negative potential difference between the control gate G and the drain D of the flash memory cell 22. For example, when an erasing voltage pulse is applied to the flash memory cell 22, the voltage of the control gate G is 10 volts, and the voltage of the drain D is +5.5 volts. With the above erasing procedure, electrons accumulated in a floating gate of the flash memory cell 22 are reduced because the electrons pass through a thin dielectric layer of the flash memory cell 22 to cause a reduction of the threshold voltage of the flash memory cell 22. When the erasing procedure is performed, the processor 34 simultaneously applies an erasing voltage pulse to each flash memory cell 22 of the flash memory array 20 to erase all of the flash memory cells 22. However, not all of the flash memory cells 22 of the flash memory array 20 have the same circuit characteristics. When the processor 34 erases the flash memory array 20, some of the flash memory cells 22 will suffer a phenomenon termed over-erasure, and over-erased flash memory cells 22 are consequently generated. An over-erased flash memory cell 22 is one in which a threshold voltage is less than 0 volts. When the flash memory array 20 has over-erased flash memory cells 22, the data reading accuracy of the flash memory array 20 is adversely affected. For example, when data stored in a flash memory cell 22 of the flash memory array 20 is to be read, if the bitline 24 connected to the flash memory cell 22 is connected to any over-erased flash memory cells 22, the bitline 24 will suffer from leakage current while reading the flash memory cell 22. This leakage current will affect the data reading accuracy. Therefore, to avoid over-erased flash memory cells 22, the processor 34 tests if there are any over-erased flash memory cells 22 after erasing the flash memory array 20. If any over-erased flash memory cells 22 are present, the processor 34 executes a correction procedure to correct the over-erased flash memory cells 22. This correction procedure returns the threshold of the over-erased flash memory cells 22 to a standard value.
Please refer to FIG.2. FIG.2 is a flow chart for erasing the flash memory array 20 and correcting any over-erased flash memory cells 22. When the flash memory circuit 10 erases the flash memory array 20, the flash memory circuit 10 determines if each flash memory cell 22 is erased by incrementally changing a row address and a column address. To ensure that a flash memory cell 22 is erased, an erasing voltage is applied to the flash memory array 20 to erase all of the flash memory cells 22. After all of the flash memory cells 22 are erased, the flash memory circuit 10 tests to see if any over-erased flash memory cells 22 were generated. If over-erased flash memory cells 22 are present, a correction procedure is performed. The above procedure is indicated in the following steps:
Step 50: Start.
Step 52: Set the row address to the first row.
Step 54: Set the column address to the first column.
Step 56: Is the flash memory cell 22 at current row and column address unerased? If yes, go to step 58. If no, go to step 70.
Step 58: Apply an erasing voltage to the flash memory array 20 to erase all flash memory cells 22.
Step 60: Set the column address to the first column.
Step 62: Are any of the flash memory cells 22 at current column address over-erased? If yes, go to step 64. If no, go to step 66.
Step 64: Apply an over-erase correction pulse to the bitline of the column address. Go to step 62.
Step 66: Increment the column address by 1.
Step 68: Is the column address the largest possible column address? If yes, go to step 54. If no, go to step 62.
Step 70: Increment the column address by 1.
Step 72: Is the column address the largest possible column address? If yes, go to step 74. If no, go to step 56.
Step 74: Increment the row address by 1.
Step 76: Is the row address at the largest possible row value? If yes, go to step 80. If no, go to step 54.
Step 80: End.
According to the above procedure, when the flash memory circuit 10 corrects over-erased flash memory cells 22, step 62 and step 64 must be repeatedly performed until the over-erased flash memory cells 22 are corrected, or until step 62 and step 64 are performed a predetermined number of times. After step 62 and step 64 have been performed a predetermined number of times, the flash memory array 20 is considered corrupted. This predetermined number of times can be set manually. Note that, after the flash memory circuit 10 completes step 64, step 62 is performed again to determine if the correction voltage pulse has corrected the over-erased flash memory cell or cells 22. Consequently, when step 62 and step 64 are performed too many times, the total checking time can become quite long. Furthermore, some over-erased flash memory cells 22 may need several more applications of the correction voltage in excess of the predetermined number of times in order to be properly corrected. The flash memory array 20 may thus be prematurely considered corrupted.
It is therefore a primary objective of the present invention to provide a circuit and associated method for correcting over-erased flash memory cells to solve the above-mentioned problems.
According to the claimed invention, a flash memory circuit has a flash memory array and a processor. The flash memory array has a plurality of erased flash memory cells. Each of the flash memory cells is respectively electrically connected to a corresponding bitline. If any over-erased flash memory cell exists in the flash memory array, the processor controls the flash memory circuit to apply a correction voltage to the bitline connected to the over-erased flash memory cell so as to correct the over-erased flash memory cell. After the correction voltage is applied to the bitline connected to the over-erased flash memory cell, if the current of the bitline is reduced to a predetermined value, the flash memory circuit stops applying the correction voltage to the bitline of the over-erased flash memory cell.
It is an advantage of the present invention that the flash memory circuit 10 avoids wasting too much time to correct any over-erased flash memory cells, and prevents an available flash memory array 20 from being prematurely discarded.
These and other objectives and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.